diff options
| author |   Claudiu Beznea <[email protected]> | 2020-07-22 10:38:11 +0300 |
|---|---|---|
| committer |   Stephen Boyd <[email protected]> | 2020-07-24 02:18:47 -0700 |
| commit | 3bf639a611a8deca7e4daa57a4df9ba4c6025249 (patch) | |
| tree | f8145f11ade0170aff66fd77d002665b4334a2e5 /drivers/clk | |
| parent | clk: at91: clk-generated: check best_rate against ranges (diff) | |
| download | wireguard-linux-3bf639a611a8deca7e4daa57a4df9ba4c6025249.tar.xz wireguard-linux-3bf639a611a8deca7e4daa57a4df9ba4c6025249.zip | |
clk: at91: clk-sam9x60-pll: fix mul mask
According to datasheet mul mask is on bits 31..24.
Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
Signed-off-by: Claudiu Beznea <[email protected]>
Reviewed-by: Alexandre Belloni <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/at91/clk-sam9x60-pll.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c index e699803986e5..3522eae2edd6 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -15,7 +15,7 @@ #include "pmc.h" #define PMC_PLL_CTRL0_DIV_MSK GENMASK(7, 0) -#define PMC_PLL_CTRL1_MUL_MSK GENMASK(30, 24) +#define PMC_PLL_CTRL1_MUL_MSK GENMASK(31, 24) #define PLL_DIV_MAX (FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, UINT_MAX) + 1) #define UPLL_DIV 2 |